The present invention relates to a synchronous semiconductor memory device and a method for controlling an input circuit of a synchronous semiconductor memory device. More particularly, the present invention pertains to the reduction of power consumption in a synchronous semiconductor memory device.
Due to the increase in the processing speed of processors, recent semiconductor memory devices, such as a synchronous DRAM (SDRAM), have data input terminals that correspond to 32 or 64 bit data. To transfer data to and from a processor, the SDRAM first receives an active command from the processor in correspondence with a synchronizing signal (CLK). When several cycles of the synchronizing signal elapses from when the SDRAM is activated, the processor provides the SDRAM with a command such as that for reading or writing data. In response to the command, the SDRAM transfers data to or from the processor.
The latency is set during a write mode during which data is written to the SDRAM. When the latency is xe2x80x9c0xe2x80x9d in the write mode, the time for receiving a write command is substantially the same as the time for receiving write data (Data-In; DIN). In other words, the SDRAM receives the write command and the write data in response to the same synchronizing signal (CLK).
As the speed of the device increases, if the SDRAM starts to accept the write data (activation of input circuit) after receiving the write command, the SDRAM may not be able to receive the write data at a predetermined time. Thus, the SDRAM must be capable of simultaneously receiving the write command and the write data.
When the SDRAM is capable of receiving a write command, the SDRAM is also capable of receiving a read command and other commands. A plurality of data input circuits must always be activated to enable the input of write data whenever receiving the write command even though the SDRAM receives other commands. Thus, when the SDRAM is in a state capable of receiving each command, current flows through the input circuits even if data is actually not written. This consumes current.
FIG. 1 shows a schematic view illustrating the shifting of states in the SDRAM.
The SDRAM has a plurality of memory banks (hereafter simply referred to as banks). The SDRAM shifts from a bank active state to other states, such as a precharge state, a bank active suspend state, a read state, or a write state. The bank forms a memory unit that may be accessed in parallel. For example, an SDRAM having two banks includes two row address input systems of a typical DRAM. This enables an A bank and a B bank of the SDRAM to independently receive active commands. FIG. 1 illustrates the shifting of states in a single bank. The arrows drawn by solid lines represent shifting performed by command inputs (manual inputs), and the arrows drawn by broken lines represent automatic shifting (automatic sequence).
The SDRAM shifts from the bank active state to a bank active suspend state, a precharge state, a write state, or a read state in a single cycle of the synchronizing signal (CLK).
Input circuits connected to terminals, which receive commands and address signals, are activated to shift the state of the SDRAM. Further, data input circuits, which are connected to data input terminals, are each activated to shift the SDRAM to the write state.
FIG. 2 is a schematic block diagram of a first example of a prior art SDRAM 10.
The SDRAM 10 includes a clock buffer 1, a flip-flop (SFF) 2, an input buffer 3, a read/write (I/O) control circuit 4, an input buffer 5, and an output buffer 6.
The clock buffer 1 receives and amplifies a clock signal CLK to generate an internal clock signal CLK1. The internal clock signal CLK1 is provided to the SFF 2. The input buffer 3 receives a mask control signal DQM. The input buffer 3 amplifies the mask control signal DQM and generates an internal mask control signal DQM1. The internal mask control signal DQM1 is provided to the SFF 2. The SFF2 latches the internal mask control signal DQM1 in synchronism with the internal clock signal CLK1 and provides the I/O control circuit 4 with the latched mask control signal DQM1 as a synchronous mask control signal DQMS.
Referring to FIG. 3, the input buffer 5 includes an AND circuit 5a that receives input data DQ and a bank active recognition signal BACT. The input buffer 5 amplifies the input data DQ when the recognition signal BACT is active and generates write data Din. The write data Din is provided to the I/O control circuit 4.
The I/O control circuit 4 provides the output buffer 6 with read data Dout, which is read from a bank (not shown). The output buffer 6 amplifies the read data Dout and generates output data DQ.
Accordingly, if the bank active recognition signal BACT is inactive and the SDRAM 19 is in an idle state, a refreshing state, or a power down state, the input buffer 5 is disabled. This decreases power consumption. However, if the recognition signal BACT is active, power consumption does not decrease.
FIG. 4 is a schematic circuit diagram of a power cut circuit 50, which decreases power consumption in an SDRAM.
The power cut circuit 50 is arranged in the SDRAM to receive a plurality of control signals generated by internal circuits (not shown). The control signals include an A bank RAS enable signal ARAE, a B bank RAS enable signal BRAE, a reading signal READB, an output enable mask signal OEMSK, and a power down signal PWDNB.
The reading signal READB goes low for a clock cycle, which has a predetermined burst length, from when a read command is provided during a read mode. The output enable mask signal OEMSK masks (prohibits use of) an internal enable signal in the read mode. The mask signal OEMSK shifts based on a data mask signal DQM.
The power down signal PWDNB shifts the SDRAM to the power down mode based on a clock enable signal CKE. A power down signal PWDNB2 for a first stage input circuit is low in the power down mode.
The power cut circuit 50 includes a first OR circuit 11, a second OR circuit 12, a NAND circuit 13, and an inverter circuit 14. The first OR circuit 11 receives the A bank RAS enable signal ARAE and the B bank RAS enable signal BRAE. The second OR circuit 12 receives the reading signal READB and the output enable mask signal OEMSK.
The NAND circuit 13 receives an output signal of the first OR circuit 11, an output signal of the second OR circuit, and a power down signal PWDNB. The inverter circuit 14 inverts the output signal of the NAND circuit 13 and generates the first stage input circuit power down signal PWDNB2.
The operation of the power cut circuit 50 will now be discussed with reference to FIG. 5.
When the power cut circuit 50 receives an A bank active command in cycle T1 of the clock signal CLK, the A bank RAS enable signal ARAE goes high. Then, when the power cut circuit 50 receives the A bank read command in cycle T2 of the power cut circuit 50, the reading signal READB goes low. The output enable mask signal OEMSK is normally low. Thus, the first stage input circuit power down signal PWDNB2 goes low, and the first stage input circuit undergoes a power cut during a read operation.
When the output enable mask signal OEMSK goes high, the power down signal PWDNB goes high and the first stage input circuit is activated. The mask signal OEMSK is generated after the data mask signal DQM goes high. Accordingly, operation of the first stage input circuit is enabled again in cycle T5 and activated before cycle T6 starts. When a write command is input during cycle T7, input write data, which is input synchronously with the write command, is acquired.
The A bank write command is input during cycle T7 to prevent bus fights of read/write data (confrontation between output signal Q3 and input signal D1) outside the SDRAM.
The time during which the SDRAM is in an idle state, a refreshing state, a power down state, or a bank active state takes up a large portion of the entire SDRAM operation time. On the other hand, the time during which the SDRAM receives a read command or a write command to read or write data takes up a small portion of the entire DRAM operation time. In other words, the time used to read or write data is short relative to the entire operation time of the SDRAM. Therefore, although the power cut circuit 50 reduces the current consumption of the data input circuits when the SDRAM is performing a read operation, the reduced current consumption is small compared with the current consumption of the entire SDRAM. Thus, the reduction of current consumption in the entire system is insufficient.
When the SDRAM is in an idle state, a refreshing state, or a power down state, the SDRAM has to shift through two or more states to enter the write state. Thus, it is impossible for the data input circuits to enter a power down state. In other words, if the data input circuits are activated when the SDRAM shifts to the bank active state, the SDRAM completes the write operation within one cycle in response to the write command.
When the (bank) activate state takes up a large portion of the operation time of the SDRAM, it is difficult for the SDRAM to complete a write operation in response to a write command within one cycle. Thus, if it is confirmed beforehand that the write operation is not performed during the period from when the SDRAM shifts from the bank active state to the precharge state, data input circuits may be inactivated, for example, by an external signal during the bank active state. This reduces power consumption during the bank active state.
However, changes in commands for shifting states in a conventional general-purpose semiconductor memory device, such as the SDRAM, makes it difficult to use the SDRAM for general purposes. Further, it becomes difficult to use the SDRAM for general purposes when adding a terminal for receiving a signal, which inactivates data input circuits and notifies that data is to be written.
It is an object of the present invention to provide a synchronous semiconductor memory device that reduces power consumption without changing command systems and adding signal input terminals. It is a further object of the present invention to provide a method for controlling input circuits of such device.
To achieve the above object, the present invention provides a method for controlling a synchronous semiconductor memory device that is operated based on a synchronizing signal. The synchronous semiconductor memory device has an input circuit for receiving write data. The method includes activating the synchronous semiconductor memory device, and selectively inactivating the input circuit based on a mask control signal for masking the write data when the synchronous semiconductor memory device is activated.
In a further perspective, the present invention is a synchronous semiconductor memory device that is operated based on a synchronizing signal. The memory device includes a memory core for storing write data. A first input circuit receives the synchronizing signal and generates an internal synchronizing signal. A second input circuit receives the write data and outputs the write data to the memory core. A third input circuit receives a mask control signal for masking the write data and outputting the mask control signal. A flip-flop circuit is connected to the first and third input circuits for generating a synchronous mask control signal based on the internal synchronizing signal. A control circuit is connected to one of the third input circuit and the flip-flop circuit for generating a control signal to selectively inactivate the second input circuit when the memory core is in an active state, based on an active recognition signal, which indicates the active state, and either one of the mask control signal and the synchronous mask control signal.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.